Senior Lead Engineer Digital Verification

Descripción del puesto

4 years of design verification experience. BS (or higher) in EE/EC/ECC Engineering Experience in mentoring junior engineer Must have excellent knowledge of computer architecture and design verification fundamentals Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies Must have experience in developing complex test bench in System Verilog using OVM/ UVM methodology Experience in Low Power Simulation/UPF setup, debug low power simulat…